1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, which in particular has transistors for different withstand voltages.
2. Background Information
With respect to a conventional semiconductor device having transistors for different withstand voltages (e.g. Japanese Laid Open Patent Application No. 2000-150665 (hereinafter to be referred to as Patent Reference I), Japanese Laid Open Patent Application No. 2000-200836 (hereinafter to be referred to as Patent Reference 2) and Japanese Laid Open Patent Application No. 2000-164726 (hereinafter to be referred to as Patent Reference 3), the transistors for different withstand voltages are formed on the same semiconductor substrate by normally using gate oxide films with different thicknesses. FIG. 1 and FIG. 2 show the manufacturing processes of a conventional semiconductor device having transistors for different withstand voltages.
Then, by conducting a thermal oxidation treatment on the surface of the semiconductor substrate 101, a gate oxide film 103A is formed on the entire surface of the semiconductor substrate 101, as shown in FIG. 1B. The gate oxide film 103A is thinner than a gate oxide film for high withstand voltage.
Next, a predetermined resist solution is spin-coated over the gate oxide film 103A after which a known photolithography process is conducted to form a resist pattern R101 only in a region on the side of high withstand voltage. Then, using the resist pattern R101 as a mask, the gate oxide film 103A in a region on the side of low withstand voltage is removed by a known etching method. Through such process, a gate oxide film 103a will remain only in the region on the high withstand voltage side, as shown in FIG. 1C. The resist pattern R101 on the remaining gate oxide film 103a is removed after the etching process is finished.
Next, by conducting a thermal oxidation treatment on the entire surface of the semiconductor substrate 101, a gate oxide film 104 with a thickness suited for low withstand voltage is formed on the entire surface, as shown in FIG. 2A. By this arrangement, a gate oxide film 103, which is a laminated product of the gate oxide film 103a and the gate oxide film 104, will be formed in the region on the high withstand voltage side. Accordingly, the thickness of the gate oxide film 103A (FIG. 1B) should be set so that the thickness of the laminated product of the gate oxide film 103a and the gate oxide film 104 is suited for high withstand voltage.
Next, a polysilicon is deposited over the entire surface of the semiconductor substrate 101 on which the gate oxide film 103a and the gate oxide film 104 are formed, and then processed by a known photolithography process and etching process to have a gate pattern 107a formed on the gate oxide film 104 in the active region AR on the low withstand voltage side, and a gate pattern 107b formed on the gate oxide film 103 in the active region AR on the high withstand voltage side, as shown in FIG. 2B.
Through the above described processes, it is possible to manufacture a semiconductor device having a transistor for low withstand voltage and a transistor for high withstand voltage formed on the same substrate.
However, according to the conventional art described above, since the gate oxide film 103A is thin, it is a problem in that the element isolating insulation films 102 in the field regions FR, particularly in the vicinity of the active regions AR, may be removed to an extent more than necessary, which may result in producing dimples on the element isolating insulation films 102. FIG. 3A shows an enlarged view of the field region FR at the process of etching the gate oxide film 103A (FIG. 1C) on the low withstand voltage side.
As shown in FIG. 3A, a dimple 101a is formed at the border between the element isolating insulation film 102 and the active region AR, and when the thermal oxidation treatment for forming the gate oxide film 104 takes place in such a state, the gate oxide film 104 will end up having a dimpled surface (i.e. a dimple 101b, FIG. 3B) as it is formed along the dimple 101a, as shown in FIG. 3B.
This dimple 101b can cause problems such as an unnecessary concentration of electric field in the dimple 101b, the gate oxide film 104 at the dimple 101b not becoming an appropriate thickness, and so forth. These problems can become triggers for other problems such as deterioration of the withstand voltage of the gate oxide film 104, etc.
Furthermore, this dimple 101b can cause materials of the gate pattern 107 (i.e. a poly-silicon 107c, FIG. 3B) to unnecessarily remain in the dimple 101b at the time of forming the gate pattern 107, as shown in FIG. 3B, and this can cause a short circuit of the gate.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method of manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.